This invention relates generally to SRAMs (static random access memories) and, more particularly, to a SRAM (static random access memory) cell having multiple ports.
A SRAM (static random access memory) is known to one of ordinary skill in the art of electronics for storing data without need for periodic refresh of data. A SRAM is comprised of an array of SRAM cells. For some applications, data of the SRAM is simultaneously shared by a plurality of memory accessing devices. For such applications, the SRAM cell of the SRAM array is a multiport SRAM cell for providing access to the data of the SRAM cell by a plurality of memory accessing devices.
FIG. 1 shows an example multiport SRAM cell 100 of the prior art as described in U.S. Pat. No. 6,097,664 to Nguyen et al. The SRAM cell 100 of FIG. 1 includes a bistable loop of a first inverter 102 and a second inverter 104. The first inverter 102 is comprised of a first PMOSFET (P-channel metal oxide semiconductor field effect transistor) 106 and a first NMOSFET (N-channel metal oxide semiconductor field effect transistor) 108 coupled between a positive power supply VCC 119 and the ground node 121. The second inverter 104 is comprised of a second PMOSFET 110 and a second NMOSFET 112 coupled between the positive power supply VCC 119 and the ground node 121. The input of the first inverter 102 is coupled to the output of the second inverter 104 at a first bistable node 114, and the input of the second inverter 104 is coupled to the output of the first inverter 102 at a second bistable node 116. The first and second bistable nodes 114 and 116 store the data of the SRAM cell 100, as known to one of ordinary skill in the art of electronics.
In addition, the SRAM cell 100 includes a third inverter 118, which is a read driver inverter, having an input coupled to the second bistable node 116. The third inverter 118 is comprised of a third PMOSFET 120 and a third NMOSFET 122 coupled between the positive power supply VCC 119 and the ground node 121. The output of the third inverter 118 is coupled to inputs of a first pass gate 124 and a second pass gate 126. First read access control signals RA1 and RA1* (the complement of RA1) are provided by a first memory accessing device to the first pass gate 124 for reading the data at the second bistable node 116, via the read driver inverter 118, of the SRAM cell 100 as output signal RD1. Second read access control signals RA2 and RA2* (the complement of RA2) are provided by a second memory accessing device to the second pass gate 126 for reading the data at the second bistable node 116, via the read driver inverter 118, of the SRAM cell 100 as output signal RD2. The first and second pass gates 124 and 126 are comprised of a pair of a PMOSFET and an NMOSFET, and such implementation of pass gates is known to one of ordinary skill in the art of electronics.
Furthermore, the SRAM cell 100 includes a third pass gate 128 coupled to the first bistable node 114. One of the first or second memory accessing devices provides first write access control signals WA1 and WA1* (the complement of WA1) to the third pass gate 128 for writing input data WD1 to the first bistable node 114 of the SRAM cell 100. The third pass gate 128 is comprised of a pair of a PMOSFET and an NMOSFET, and such implementation of a pass gate is known to one of ordinary skill in the art of electronics.
Additionally, a pass transistor 130 is coupled to the first bistable node 114. A memory accessing device provides access control signal WA2 to the pass transistor 130 for either reading data R/WD2 from the first bistable node 114 of the SRAM cell 100 or for writing data R/WD2 to the SRAM cell 100. For example, the memory accessing device coupled to the pass transistor 130 includes portions 132 and 136 of a serial boundary scan subsystem. The portion 136 of the serial boundary scan subsystem functions to serially provide data R/WD2 to be written into the SRAM cell 100 or alternatively to serially receive data R/WD2 read from the SRAM cell 100, from or into a respective location 138 of the portion 136 of the serial boundary scan subsystem. The portion 132 of the serial boundary scan subsystem functions to serially provide the access control signal WA2 from the respective location 134 of the portion 132 of the serial boundary scan subsystem.
The portions 132 and 136 of the serial boundary scan subsystem are used for writing and reading initial configuration data to be stored by the SRAM cell 100, as described in U.S. Pat. No. 6,097,664 to Nguyen et al. The portions 132 and 136 of the serial boundary scan subsystem are typically already present within a memory system such that such initial configuration data may be stored into the SRAM cell 100 without significant added circuitry of the memory system. In addition, by using a single pass transistor 130 (instead of a two-MOSFET pass gate), the metal lines from the portions 132 and 136 of the serial boundary scan subsystem for writing and verifying the initial configuration data within the SRAM cell 100 are advantageously minimized.
In the SRAM cell 100, the first PMOSFET 106 and the first NMOSFET 108 of the first inverter 102 are sized to be larger than the second PMOSFET 110 and the second NMOSFET 112, respectively, of the second inverter 104. Thus, the W/L (i.e., the width over length) ratio of the first PMOSFET 106 is larger than the W/L (i.e., the width over length) ratio of the second PMOSFET 110, and the W/L (i.e., the width over length) ratio of the first NMOSFET 108 is larger than the W/L (i.e., the width over length) ratio of the second NMOSFET 112.
In that case, the MOSFETs 106 and 108 of the first inverter 102 have higher transconductance, GM, than that of the MOSFETs 110 and 112 of the second inverter 104. As a result, for writing data into the SRAM cell 100, the write data via the third pass gate 128 or via the pass transistor 130 is applied on the input (i.e., the first bistable node 114) of the first inverter 102 rather than on the input of the second inverter 104. The output 116 of the first inverter 102 with the MOSFETs 106 and 108 having higher transconductance over-powers the output 114 of the second inverter 104. Thus, the write data for the write operation is applied on the input (i.e., the first bistable node 114) of the first inverter 102 for proper write operation when the MOSFETs 106 and 108 of the first inverter 102 have higher transconductance than that of the MOSFETs 110 and 112 of the second inverter 104.
Because the MOSFETs of the first and second inverters 102 and 104 are differently sized, the multiports comprising the first, second, and third pass gates 124, 126, 128 and the pass transistor 130 are each single-ended, accessing only one of the first or second bistable nodes 114 and 116. The ports comprising the first and second pass gates 124 and 126 access the single second bistable node 116 via the read driver inverter 118 for reading data from the SRAM cell 100. The ports comprising the third pass gate 128 and the pass transistor 130 access the single first bistable node 114 for writing data to the SRAM cell 100. The port comprising the pass transistor 130 also accesses the single first bistable node 114 for reading data from the SRAM cell 100.
A disadvantage of the SRAM cell 100 of FIG. 1 is that each of the multiports comprising the first, second, and third pass gates 124, 126, 128 does not have the dual functionality of both reading and writing to the SRAM cell 100. The ports of the SRAM cell 100 comprising the first and second pass gates 124 and 126 are read only, and the port comprising the third pass transistor 128 is write only. In addition, because the ports of the SRAM cell 100 comprising the first, second, and third pass gates 124, 126, and 128 and the pass transistor 130 are single-ended, such ports are prone to signal deterioration from noise.
FIG. 2 shows another multiport SRAM cell 150 for providing both read and write functionality for each port that is single-ended. Elements having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function. The SRAM cell 150 of FIG. 2 includes the bistable loop comprised of the first inverter 102 and the second inverter 104 as described for the SRAM cell 100 of FIG. 1. In addition, the third inverter 118 is coupled to the second bistable node 116 for providing access to the data of the SRAM cell 150. In addition, the MOSFETs of the first and second inverters 102 and 104 of FIG. 2 are differently sized as already described herein with reference to FIG. 1.
The SRAM cell 150 of FIG. 2 includes a first pass gate 152, a second pass gate 154, and a third pass gate 156 comprising a first port. The SRAM cell 150 also includes a fourth pass gate 158, a fifth pass gate 160, and a sixth pass gate 162 comprising a second port. A first memory accessing device provides RW1 and RW1* (the complement of the RW1 signal) control signals for accessing the SRAM cell 150. In addition, the first memory accessing device provides WA1 and WA1* (the complement of the WA1 signal) control signals for accessing the first bistable node 114 of the SRAM cell 150 to write data R/WD1 into the SRAM cell 150. Furthermore, the first memory accessing device provides RA1 and RA1* (the complement of the RA1 signal) control signals for accessing the second bistable node 116 via the read driver inverter 118 of the SRAM cell 150 to read data R/WD1 from the SRAM cell 150.
Similarly, a second memory accessing device provides the RW2 and RW2, (the complement of the RW2 signal) control signals for accessing the SRAM cell 150. In addition, the second memory accessing device provides WA2 and WA2* (the complement of the WA2 signal) control signals for accessing the first bistable node 114 of the SRAM cell 150 to write data R/WD2 into the SRAM cell 150. Furthermore, the second memory accessing device provides RA2 and RA2* (the complement of the RA2 signal) control signals for accessing the second bistable node 116 via the read driver inverter 118 of the SRAM cell 150 to read data R/WD2 from the SRAM cell 150.
The pass transistor 130 in FIG. 2 comprises a third port similar to the pass transistor 130 of FIG. 1 for providing read and write access to the first bistable node 114 of the SRAM cell 150. A third memory accessing device provides the access control signal SA to the pass transistor 130 for accessing the first bistable node 114 to read or write data R/WSD from or to the SRAM cell 150.
Because the MOSFETs of the first and second inverters 102 and 104 of FIG. 2 are differently sized, the multiports comprising the plurality of pass gates 152, 154, 156, 158, 160, and 162 and the pass transistor 130 are each single-ended accessing only one of the first or second bistable nodes 114 and 116 for each one of the read or write function, and such ports are prone to signal deterioration from noise. In addition, the SRAM cell 100 of FIG. 1 is comprised of thirteen MOSFETs, and the SRAM cell 150 of FIG. 2 is comprised of nineteen MOSFETs. When the SRAM cell is used in application within a register file comprised of thousands of SRAM cells, the number of MOSFETs for implementing a SRAM cell is not as critical. However, when the SRAM cell is used in application with a data processor within a memory system comprised of millions of SRAM cells, the number of MOSFETs for implementing a SRAM cell is desired to be minimized for in turn minimizing the area of the memory system comprised of such SRAM cells.
Thus, a SRAM cell is desired that provides a single-ended port and a differential port with a minimum number of transistors.
Accordingly, in a general aspect of the present invention, a SRAM cell is implemented with at least one differential port and at least one single-ended port.
In one example embodiment, a multiport SRAM (static random access memory) cell comprises a bistable loop of a first inverter and a second inverter. An input terminal of the first inverter is coupled to an output terminal of the second inverter at a first bistable node, and an input terminal of the second inverter is coupled to an output terminal of the first inverter at a second bistable node. In addition, a single-ended port is coupled to one of the first bistable node or the second bistable node, and a differential port is coupled to both of the first and second bistable nodes.
In another aspect of the present invention, a multiport SRAM (static random access memory) cell comprises a bistable loop of a first inverter and a second inverter. An input terminal of the first inverter is coupled to an output terminal of the second inverter at a first bistable node, and an input terminal of the second inverter is coupled to an output terminal of the first inverter at a second bistable node. A single-ended port is coupled to one of the first bistable node or the second bistable node and is operable to both read data from and write data to the coupled bistable node through a same transistor. A differential port is coupled to both of the first and second bistable nodes and is operable to both read data from and write data to the coupled bistable nodes through a same pair of transistors.
In a further aspect of the present invention, a multiport SRAM (static random access memory) cell comprises a bistable loop consisting of a first CMOS inverter having first and second transistors and a second CMOS inverter having third and fourth transistors. An input terminal of the first inverter is coupled to an output terminal of the second inverter at a first bistable node, and an input terminal of the second inverter is coupled to an output terminal of the first inverter at a second bistable node. A single-ended port consists of a fifth transistor coupled to one of the first bistable node or the second bistable node, and a differential port consists of a sixth transistor coupled to the first bistable node and a seventh transistor coupled to the second bistable node.
In yet a further aspect of the present invention, a method of accessing data within an SRAM (static random access memory) cell comprises providing a single-ended port within the SRAM cell and providing a differential port within the SRAM cell. In addition, data within the SRAM cell is accessed through the single/ended port simultaneously with accessing data within the SRAM cell through the differential port.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.